
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:26:13 04/26/2012
-- Design Name:   proyecto_aic
-- Module Name:   C:/AyudaDatapath/proyecto_aic/tb_proyecto.vhd
-- Project Name:  proyecto_aic
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: proyecto_aic
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_proyecto_vhd IS
END tb_proyecto_vhd;

ARCHITECTURE behavior OF tb_proyecto_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT proyecto_aic
	PORT(
		clk_i : IN std_logic;
		clr_i : IN std_logic;
		int_req : IN std_logic;          
		int_ack : OUT std_logic;
		data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
      data_word_o : out  STD_LOGIC_VECTOR (7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk_i :  std_logic := '0';
	SIGNAL clr_i :  std_logic := '0';
	SIGNAL int_req :  std_logic := '0';

	--Outputs
	SIGNAL int_ack :  std_logic;
	SIGNAL data_addr_o : STD_LOGIC_VECTOR (7 downto 0);
	SIGNAL data_word_o :   STD_LOGIC_VECTOR (7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: proyecto_aic PORT MAP(
		clk_i => clk_i,
		clr_i => clr_i,
		int_req => int_req,
		int_ack => int_ack,
		data_addr_o => data_addr_o,
		data_word_o => data_word_o 
		
		
	);

   ck : PROCESS
	BEGIN
		clk_i <= '1';
		wait for 50 ns;
		clk_i <= '0';
		wait for 50 ns;
	END PROCESS;
	
	
	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		
		clr_i <= '1';
		wait for 100 ns;
		clr_i <= '0';
		wait for 100 ns;
		wait for 100 ns;
		wait for 100 ns;
		
		--assert int_ack = '0' report " primer test total";
		wait for 100 ns;
		wait for 100 ns;
		wait for 100 ns;
		wait for 100 ns;
		wait for 100 ns;
		wait for 100 ns;
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;
